1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a test circuit based on scan registers, and a method of testing the semiconductor integrated circuit.
2. Description of the Related Art
As a technique for testing a semiconductor integrated circuit, there has been one called “shift scan system” wherein scan registers are inserted among logic circuit blocks which perform the functional operations of the integrated circuit, and in the test mode of the integrated circuit, the scan registers are connected in the shape of a chain so as to supply testing data to the respective logic circuit blocks and to derive output data from them.
The test circuit of such a shift scan system, however, has had the problem that, as the number of the logic circuit blocks becomes larger, the number of the scan registers to constitute the scan chain enlarges more, so a long time is expended in inputting and outputting the test data.
A semiconductor integrated circuit having a test circuit is disclosed in Japanese unexamined published patent application JP-A-2000-258500.
The semiconductor integrated circuit is constructed of a circuit to-be-tested 102, scan data input terminals 151, 152, scan data output terminals 161, 162, a connection alteration circuit 103, and a code compression circuit 104.
The circuit to-be-tested 102 has scan chains 110, 120, 130, 140, in which scan registers 111-113, 121-123, 131-133, 141-143 are respectively connected so as to be capable of inputting and outputting scan data. Besides, the circuit to-be-tested 102 has partial circuits 171, 172 which are independent like combinational circuits. Here, the scan chains 110, 120 and those 130, 140 belong to the partial circuit 171 and the partial circuit 172, respectively.
The connection alteration circuit 103 branches the scan data input terminal 151 to the scan chains 110 and 130 at a branch point 153, and branches the scan data input terminal 152 to the scan chains 120 and 140 at a branch point 154. The code compression circuit 104 takes the exclusive logic of the scan chains 110 and 130 by a logic gate 163 and delivers it to the scan data output terminal 161, and takes the exclusive logic of the scan chains 120 and 140 by a logic gate 164 and delivers it to the scan data output terminal 162.
With such a semiconductor integrated circuit, the scan data inputted to, for example, the scan data input terminal 151 is simultaneously supplied to the two scan chains 110, 130. Besides, the scan data transferred by successively shifting along the scan chains 110, 130 have their exclusive logic taken by the logic gate 163, and the resulting data is outputted from the scan data output terminal 161. Thus, the test of the scan chains 110-140 being the circuit to-be-tested 102 can be performed in a short time.
As stated before, the semiconductor integrated circuit of the conventional shift scan system has had the problem that, with the enlargement of a circuit scale, a long time is expended in inputting and outputting test data. On the other hand, with the semiconductor integrated circuit disclosed in the above Japanese patent laid open, the same scan data is inputted to the two scan chains 110, 130, and any desired data cannot be held in the individual scan registers 111-113, 131-133. It is consequently impossible to test the operation of each logic circuit by supplying any desired test data to the logic circuit.